1. Field of Invention
The present invention relates to a fabrication method of integrated circuits. More particularly, the present invention relates to a method of dual salicide (self-aligned silicide) for integrated circuits.
2. Description of Related Art
For an integrated circuit composed of memory and logic circuits on one chip, meeting the different electrical requirements of memory and logic circuits at the same time while increasing the number of photo-mask used to a minimum extent are two important technical issues in the fabrication of semiconductor integrated circuits. For transistors in the memory region, current leakage is the most important problem that needs to be avoided, because it will increase the refresh frequency to decrease the memory efficiency. Therefore, decreasing sheet resistance of the transistors"" source/drain is less important than avoiding the current leakage of the transistors"" source/drain. However, for transistors in the logic region, the operation speed is the most important requirement. Therefore, decreasing the sheet resistance of the transistors"" source/drain is very important.
How to effectively make use of the self-aligned silicide (abbreviated as salicide) process to selectively form metal silicide respectively on transistors"" gates, sources and drains to meet the different requirements of memory and logic circuits is a problem that needs to be solved. Usually, metal silicide (MxSiy) possesses much lower resistance than doped silicon. Furthermore, the salicide process has been developed to form metal silicide only on the silicon""s surface. Thus, the salicide process is usually used to decrease the resistance of both the polysilicon gate and the source/drain.
The invention provides a method of forming dual salicides for integrated circuits. A mask layer is formed over a substrate having a first transistor, a second transistor and a third transistor thereon. The top surface of the first transistor""s gate is higher than those of the second and the third transistors"" gates. The mask layer is patterned to expose the top surface of the second transistor""s gate, source and drain. First metal silicides are formed respectively on the top surfaces of the second transistor""s gate, source and drain. A dielectric layer is formed over the substrate, and the top surface of the dielectric layer is higher than that of the first transistor""s gate. The dielectric layer higher than the top surfaces of the second and the third transistors"" gates is removed to expose the top surfaces of the first, the second and the third transistors"" gates. Second metal silicides are formed respectively on the top surfaces of the first and the third transistors"" gates.
The invention also provides another method of forming dual salicides for integrated circuits. A mask layer is formed over a substrate having a first transistor, a second transistor and a third transistor thereon. The top surface of the first transistor""s gate is higher than those of the second and the third transistors"" gates. The mask layer is patterned to expose the top surface of the second transistor""s gate, source and drain. First metal silicides are formed respectively on the top surfaces of the second transistor""s gate, source and drain. A dielectric layer is formed over the substrate, and the top surface of the dielectric layer is higher than that of the first transistor""s gate. The dielectric layer that is higher than the top surfaces of the second and the third transistors"" gates is removed to expose the top surfaces of the first, the second and the third transistors"" gates. A second mask layer is formed over the substrate. The second mask layer is patterned to expose the top surface of the first transistor gate. A second metal silicide is formed on the top surface of the first transistor""s gate.
The first transistor can be located in, for example, the memory region, and the second and the third transistors can be located in, for example, the logic region. The first and the second metal silicides are, for example, titanium silicide, cobalt silicide or nickel silicide. The dielectric layer high than the top surfaces of the second and the third transistors"" gates is removed by, for example, chemical mechanical polishing and etching back.
As embodied and broadly described herein, the invention provides a method of separately forming metal silicides on different transistors"" gates, sources and drains. Therefore, the optimum requirement of transistors on different regions can be met.
It is to be understood that both the foregoing general description and the following detailed description are examples only, and are intended to provide further explanation of the invention as claimed.